Name [ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming

File Type video

Size 1.33GB

UpdateDate 2024-9-27

hash *****17FB5C9D11777AF7048498F5CA4DA56A4E

Hot 7

Files Get Bonus Downloads Here.url | 180B ~Get Your Files Here !/01 - Introduction/001 Preview.mp4 | 27.07MB ~Get Your Files Here !/01 - Introduction/001 Preview_en.vtt | 4.55KB ~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4 | 6.21MB ~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication_en.vtt | 1.07KB ~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication.mp4 | 24.19MB ~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication_en.vtt | 2.76KB ~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication.mp4 | 5.82MB ~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication_en.vtt | 970B ~Get Your Files Here !/02 - Introduction to UART/001 What is UART.mp4 | 6.91MB ~Get Your Files Here !/02 - Introduction to UART/001 What is UART_en.vtt | 1.36KB ~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART.mp4 | 3.30MB ~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART_en.vtt | 632B ~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART.mp4 | 29.82MB ~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART_en.vtt | 4.83KB ~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART.mp4 | 10.37MB ~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART_en.vtt | 2.78KB ~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator.mp4 | 11.73MB ~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator_en.vtt | 2.07KB ~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator.mp4 | 93.15MB ~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator_en.vtt | 10.26KB ~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter.mp4 | 6.72MB ~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter_en.vtt | 1.39KB ~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver.mp4 | 5.54MB ~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver_en.vtt | 1.22KB ~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment.mp4 | 22.12MB ~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment_en.vtt | 3.50KB ~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4 | 531.38MB ~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt | 45.57KB ~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4 | 326.25MB ~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt | 28.21KB ~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4 | 251.42MB ~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt | 25.90KB ~Get Your Files Here !/Bonus Resources.txt | 386B